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Department of Electrical Engineeringclos

A performance analysis for interconnections of 3D ICs with frequency-dependent TSV model in S-parameter

In this study, the effects of the frequencydependent characteristics of through-silicon vias (TSVs) on the performance of 3D ICs are examined by evaluating a typical interconnection structure, which is composed of 32-nm CMOS inverter drivers and receivers connected through TSVs. The frequency-domain model of TSVs is extracted in S-parameter from a 3D electromagnetic (EM) method, where the dimensional variation effect of TSVs can be accurately considered for a comprehensive parameter sweep simulation. A parametric analysis shows that the propagation delay increases with the diameter and height of the TSVs but decreases with the pitch and liner thickness. We also investigate the crosstalk effect between TSVs by testing different signaling conditions. From the simulations, the worst signal integrity is observed when the signal experiences a simultaneously coupled transition in the opposite direction from the aggressor lines. Simulation results for nine-TSV bundles having regular and staggered patterns reveal that the proposed method can characterize TSV-based 3D interconnections of any dimensions and patterns.close0

An extemal-capacitor-less low-dropout regulator with less than -36dB PSRR at all frequencies from 10kHz to 1GHz using an adaptive supply-ripple cancellation technique to the body-gate

An external capacitor-less low-dropout regulator (LDO) that provides high power-supply rejection ratio (PSRR) at all low-to-high frequencies was presented. The LDO was designed to have the dominant pole, ??D, at the gate of the passtransistor, VG, to secure stability without an external capacitor, even when the load current was large. Using the proposed adaptive supply-ripple cancellation (ASRC) technique, where the ripples copied from the supply are injected adaptively to the body-gate, the PSRR-hump of conventional LDOs with ??D at VG can be suppressed significantly. Since the ASRC continues to adjust the magnitude of the injecting ripples, the LDO of this work is able to maintain high PSRRs, irrespective of the amount of the load current, IL, or the dropout voltage, VDO. The proposed LDO was fabricated in a 65-nm CMOS process, and it had an input voltage of 1.2V. When having a 240-pF load capacitor, the measured PSRRs were less than –36dB at all frequencies from 10kHz to 1GHz, despite changes in IL and VDO. The active area was 0.087mm2 including the 240-pF load capacitor, and the total power consumption was 360??W

An external-capacitor-less high-PSR low-dropout regulator using an adaptive supply-ripple cancellation technique to the body-gate

This work presents an external-capacitor-less low-dropout regulator (LDO) that provides high power-supply rejection (PSR) at all low-to-high frequencies. Using the proposed adaptive supply-ripple cancellation (ASRC) technique, where the ripples copied from the supply are injected adaptively to the body-gate, the PSR-hump of conventional LDOs can be suppressed significantly. The proposed LDO was fabricated in a 65-nm CMOS process, and the measured PSRs were less than -36dB at all frequencies from 10kHz to 1GHz, despite changes in a load current (Zl) and a dropout voltage (Fdo)

A PVT-Robust and Low-Jitter Ring-VCO-Based Injection-Locked Clock Multiplier with a Continuous Frequency-Tracking Loop Using a Replica-Delay Cell and a Dual-Edge Phase Detector

A low-jitter, ring-type voltage-controlled oscillator (VCO)-based injection-locked clock multiplier (ILCM) with a continuous frequency-tracking loop (FTL) for process-voltage-temperature (PVT)-calibration is presented. Using a single replica-delay cell of the VCO that provides the intrinsic phase information of the free-running VCO, the proposed FTL can continuously track and correct frequency drifts. Therefore, the proposed ILCM can calibrate real-time frequency drifts due to voltage or temperature variations as well as static frequency deviations due to process variations. Since the FTL provided an additional filtering of in-band VCO noise, the ILCM was able to achieve excellent jitter performance over the PVT variations, while it was based on a ring-VCO. The proposed ILCM was fabricated in a 65 nm CMOS process. When injection locked, the RMS-jitter integrated from 10 kHz to 40 MHz of the 1.20 GHz output signal was 185 fs. The proposed PVT-calibrator regulated the degradations of jitter to less than 5% and 7% over temperatures and supply voltages, respectively. The active area was $text {0.06 mm}^{2}$ and total power consumption was 9.5 mW.clos

A 0.5V-VIN, 0.29ps-Transient-FOM, and Sub-2mV-Accuracy Adaptive-Sampling Digital LDO Using Single-VCO-Based Edge-Racing Time Quantizer

This work presents a digital LDO using a single-VCO-based edge-racing (SVER) time quantizer to achieve fast transient and high accuracy concurrently. As the SVER scales the sampling frequency dynamically according to the magnitude of the error in the output voltage, the transient response can be improved without the increase in the power consumption in the steady state. Since the SVER uses a single VCO, the accuracy of the output can be high against local mismatches. In measurement, this LDO achieved a 0.29 ps-transient FOM and a sub-2 mV accuracy under 0.5-V supply

An External Capacitorless Low-Dropout Regulator With High PSR at All Frequencies From 10 kHz to 1 GHz Using an Adaptive Supply-Ripple Cancellation Technique

Herein is presented an external capacitorless low-dropout regulator (LDO) that provides high-power-supply rejection (PSR) at all low-to-high frequencies. The LDO is designed to have the dominant pole at the gate of the pass transistor to secure stability without the use of an external capacitor, even when the load current increases significantly. Using the proposed adaptive supply-ripple cancellation (ASRC) technique, in which the ripples copied from the supply are injected adaptively to the body gate, the PSR hump that appears in conventional gate-pole-dominant LDOs can be suppressed significantly. Since the ASRC circuit continues to adjust the magnitude of the injecting ripples to an optimal value, the LDO presented here can maintain high PSRs, irrespective of the magnitude of the load current I-L, or the dropout voltage V-DO. The proposed LDO was fabricated in a 65-nm CMOS process, and it had an input voltage of 1.2 V. With a 240-pF load capacitor, the measured PSRs were less than -36 dB at all frequencies from 10 kHz to 1 GHz, despite changes of I-L and V-DO as well as process, voltage, temperature (PVT) variations

A 320??V-Output Ripple and 90ns-Settling Time at 0.5V Supply Digital-Analog-Hybrid LDO Using Multi-Level Gate-Voltage Generator and Fast-Decision PD Detector

This work presents a digital-analog-hybrid LDO (HLDO) using a multi-level gate-voltage generator (MGG) to achieve a small output ripple (VR) and a fast-transient response. Using the MGG that can partially turn on transistors in the power MOSFET (Mp) and thus reduce Mp's LSB current, VR was limited to less than 320 ??V. Also, a fast-decision PD detector having a non-zero decision level expedited the switching of transistors in Mp, thereby reducing the settling time to less than 90 ns

30.9 A 140fs rms -Jitter and -72dBc-Reference-Spur Ring-VCO-Based Injection-Locked Clock Multiplier Using a Background Triple-Point Frequency/Phase/Slope Calibrator

An injection-locked clock multiplier (ILCM) is one of the best options to generate low-jitter high-frequency signals, while using a ring VCO. In the sense that the VCO jitter is removed periodically by the reference clock, S REF , an MDLL also can be considered to be an ILCM. However, the most critical problem of ILCMs is that their jitter performance can degrade easily due to PVT. To ensure ultra-low jitter robustly, ILCMs must be equipped with background calibration that continuously adjusts the free-running frequency of the VCO, f VCO , to stay close to the target frequency, Nf REF , where N is the multiplication factor and f REF is the frequency of S REF , thereby minimizing the frequency error. To date, various calibrating methods have been developed, and many of them [1]-[4] successfully tracked f VCO and prevented the degradation in random jitter, but none of the ILCMs succeeded in reducing reference spurs to a level comparable to that of PLLs. This is because even a slight phase error of an edge of the output signal, S OUT , could result in large reference spurs [1]. There are three major causes of the phase error, the first of which is the frequency error due to drifts in f VCO away from Nf REF , which is the main target of prior calibrators. The second cause is the phase offset, which is generated due to any systematic errors of calibrators, such as mismatches in delay cells, input offsets of phase detectors, and limited resolution of digital circuits. Recently, state-of-the-art ILCMs [3], [4] successfully addressed these two causes, but they still could not reduce reference spurs to less than -65dBc. This is because, to date, none of the ILCMs has considered the third cause, i.e., the slope modulation of the edges of S OUT , which occurs due to the periodic injection of S REF

Modified submental intubation techniques for maxillofacial surgery - A report of five cases -

Background Submental intubation has been the recommended airway management procedure for maxillofacial surgery since proposed by Altemir in 1986. We adopted various submental intubation modifications based on modified intubation protocols and report on the effectiveness and problems of each modified method. Case Among a total of 13 submental intubation cases during the last five years, five representative methods are described. The proximal end of the endotracheal tube was protected by a nelaton catheter in case 1, by a suction connector in case 2, and by a dental needle cap in case 3. In case 4, a nasal speculum was used to expand a single route, and in case 5, a laparoscopic trocar was used to secure a single route. Conclusions Use of a laparoscopic trocar might be the most effective way to obtain a single submental route. However, considering cost, use of a nasal speculum is also an effective suboptimal solution